Serial two{3 s complementer

ABSTRACT

The present invention relates to a serial two&#39;&#39;s complementer whose logical design, by the preferential use of NAND devices and other measures, provides a minimum geometry configuration, in an implementation using metal oxide semiconductor field effect transistors with large scale integration. The two&#39;&#39;s complement function is achieved by a binary storage element implemented by an inverter, two NAND gates with two half bit dynamic delays and by an exclusive NOR gate implemented by a NAND gate and a composite NAND-OR configuration. The binary storage element and exclusive NOR gate are interconnected to invert the serial bit stream after the occurrence of the first one to produce the two&#39;&#39;s complement.

United States Patent 11 1 Irwin et al.

[451 Oct. 21, 1975 i 1 SERIAL TWOS COMPLEMENTER [75] Inventors: John M.Irwin, Clay; Noble R. Powell, Syracuse, both of N.Y.

[73] Assignee: General Electric Company,

Syracuse, NY.

[22] Filed: Nov. 4, 1974 [21] Appl. No.: 520,542

[57] ABSTRACT The present invention relates to a serial twoscomplementer whose logical design, by the preferential use of NANDdevices and 'other measures, provides a minimum geometry configuration,in an implementation [52] US. Cl. 235/164; 307/207 u g/ ta oxide s i dut r f ld ff t transis- [51] Int. Cl. G06F 5/02; 1103K 13/25 tors with lag s al integ ati n. The t os comple- Field f Search 235/164; 307/207,213; ment function is achieved by a binary storage element 340/347 DDimplemented by an inverter, two NAND gates with two half bit dynamicdelays and by an exclusive NOR [56] References Cited gate implemented bya NAND gate and a composite UNITED STATES PATENTS NAND-OR configuration.The binary storage element and exclusive NOR gate are interconnected toinvert 2,941,719 6/1960 Gloess et al. 235/164 the Serial bit Streamafter the Occurrence of the first one to produce the twos complement.

8 Claims, 4 Drawing Figures EXCLUSIVE l NOR 5 ZourPur INPUT STORAGE 6 RELEMENT r H be 1 l2 RESET Ronmom.

US. Patent Oct. 21, 1975 SERIAL TWOS COMPLEMENTER BACKGROUND OF THEINVENTION:

1. Field of the Invention w The present invention relates to-the fieldof digital computation and moreparticularly 'to sequential logic used toform a twos complement of a number typically for effecting a signchange. The invention relates to logic particularly adapted to largescale integration;

2. Description of the Prior Art The properties of the twos complement ofa binary number are well known. Several algorithms are known forserially forming the complement of a binary number in which the leastsignificant bit occurs first in time, and the word terminates with asign bit as the most significant bit.

The large scale integration in MOS technology of certain logic functionsis treated in a book entitled MOS Integrated Circuits, edited by WilliamM. Penney and Lillian Lau, Van Nostrand Reinhold Company, New York 1972.g

The logic by which many algorithms have been implemented is not wellsuited for large scale integration. Many applications also require anenabling control and variable word length capability with contiguousarrangement of data words.

SUMMARY OF THE INVENTION Accordingly, it is an object of the presentinvention to provide an improved serial twos complementer.

It is another object of the present invention to providean improvedserial twos complementer of minimum geometry when fabricated in largescale integration.

It is a further object of the present invention to provide an improvedserial twos complementer having a minimum geometry when implementedusing metal oxide semiconductor field effect transistor devices.

These and other objects of the invention are achieved in a novelcombination for serially forming the twos complement of a binary numberof variable word length with the least significant bit first in time.The invention comprises a binary storage element having set and resetinput connections and a complementary output connection. Means areprovided to reset the binary storage element by the time of the leastsignificant bit for each word in the serial bit stream and the set inputconnection is coupled to the apparatus input terminal. The binarystorage element responds to thefirst one in the input bit stream andproduces-a change in output after a one bit delay. An exclusive NOR isalso provided having two input connections and an output connection. Oneinput connection is coupled to the apparatus input terminal and theother to the complementary output of the binary storage element. Theoutput connection from the exclusive NOR is coupled to the apparatusoutput terminal. The exclusive NOR inverts the input bit stream when thecomplementary output of the binary storage element goes to thezerostate. The twos complement of the serial input number appears at theapparatus output terminal.

In accordance with an aspect of the invention the binary storage elementcomprises an inverter, a first NAND gate having two inputs and anoutput, a dynamic one bit time delay, and a second NAND gate having twoor three inputs and an output. The inverter is coupled between theapparatus input terminal and one input of the first NAND gate and theoutput of the first NAND gate is coupled through the delay to one secondNAND gate provides a-reset input. The output of the second NAND gate iscoupled back to the other input of the first NAND gate and to the inputof the exclusive NOR gate.

Inaddition, the exclusive NOR gate comprises a third NAND gate, a fourthNAND gate, and an OR gate, each having two inputs and an output. Oneinput connection of the third NAND gate and the OR gate are connected tothe output of the binary storage element. Another input of the thirdNAND gate and the OR gate are connected to the apparatus input terminal.The output connections of the third NAND gate and the OR gate areconnected to the respective inputs of the fourth NAND gate. The outputof the fourth NAND gate is connected to the apparatus output terminal.

In accordance with another aspect of the invention, the second NAND gateis provided with an input for the reset function which resets the gatejust prior to the least significant bit in the input bit stream. It mayalso be provided with an input for the control function which enables ordisables the twos complement function of the apparatus.

The twos complementer is preferably carried out with MOSFET (metal oxidesemiconductor field effect transistor) technology and'fabricated inlarge scale integrated form.

BRIEF DESCRIPTION OF THE DRAWING The novel and distinctive features ofthe invention are set forth in the claims appended to the presentapplication. The invention itself, however, together with furtherobjects and advantages thereof may best be understood by referenceto'the following description and accompanying drawings, in which:

FIG. 1 is a block diagram in simplest form of a serial twos complementerin accordance with the invention;

FIG. 2 is a logic diagram of the serial twos complementer;

FIG. 3 is a circuit diagram of a serial twos complementer employingmetal oxide semiconductor field effect transistors and suitable forfabrication in large scale integrated circuit format; and

FIG. 4 is a chart of the transconductances of the field effecttransistors used in the circuit diagram of FIG. 3.

DESCRIPTION OF A PREFERRED EMBODIMENT A serial twos complementer inaccordance with the invention is shown in the simple block diagram ofFIG. 1. Its two principal parts are a binary storage element 11 and anexclusive NOR gate 12. The binary storage element has set and resetinput connections, a control input and a complementary outputconnection. The exclusive NORgate 12 is provided with a pair of inputconnections and a single output connection. Input signals from a-source10 are applied to the set terminal of the binary storage element and toone input of the exclusive NOR gate 12. The complementary output of thebinary storage element 11 is applied to the other input of the exclusiveNOR gate 12. The output of the exclusive NOR gate is coupled to theoutput 13. The twos complement of the number applied to the input 10appears at the output 13.

The twos complement of a binary number is of interest when it is desiredto effect a sign change such as for subtraction. In such usage, thenumber is available in binary form, with the bits arranged in order fromthe least significant bit to the most significantbit, with a sign bitbeing defined as the most significant bit, and

pleted with t he-'NAND. gate 23, the OR gate 24 and the NAND gate 25,which perfbrm the function of the exclusive NOR"gate 1 2 of FIG. 1.

The elements l4" -'20 "constituting the binary storage the word lengthmay be variable. In the case of sub- 5 element 11are-interconnected inthe following mantracting, the twos complement of the subtrahend mayner. The input isapplied to the input terminal of the be formed and thensubstituted for the number and inverter 14 whose output terminal iscoupled to one of added to the minuend. This will have the effect in theth two inputs of the NAND gate 15. The output of the computed result ofsubtraction. NAND gate .15 is applied to the input of a field effect Theapparatus blocked out in FIG. 1 is designed to 10 transistor acting as atransmission gate,l6. The output form the twos complement of a digitalnumber of vari- 0f the 16 is coupled t e input of the inverter able wordlength, with the least significant bit first in The inverter NAND g 15,and the gate (8) time followed by successively more significant bits and0f the PET transmission g 16 e eieeked .ih y having 'a sign bit as themost significant bit. When such ehl'ohism with the bit Stream yConnection to the 1 2 a number is available at the input 10, it will beapplied eioek T p t of the ihyerter 17 is coupled to to the set terminalof the binary storage element 11 and the input of a Second PETtransmission gate The to one input terminal of the exclusive NOR 12. Ifthe Output of the second PET is eohheeted to h input of i i i bit i 0 nochange in State occurs i the binary the inverter 19. The inverter 17 andthe transmission storage element 11, and a 0 appears at the output ofthe gate 18 are clocked at ah approximately 95bit deiay exclusive NOR12. If the second bit is also a 0, no with respect to the bit-Stream yeehheetieh t0 the 4 2 change in State occurs If the third bit is a 1 achange clock bus. The output of the inverter 19 is then coupled instateoccurs in the binary storage element at the end to one of the threeinputs of e NAND gate The of the bit time, and at the end of the bittime, the cominverter 19 and the NAND gate 20 are both clocked yplementary 6 output provides a O: The third bit is connection to the bclock u The other t Q P passed unchanged as a l at the output of theexclusive of the NAND gate 20 form respectively the Peihts NOR a fourthbit is O, the binary Storage element resetting the binary storageelement and for application mains at O, and the exclusive NOR nowchanges the of the two eoihplemeht The output of the input bit from a 0to a 1. From the fourth bit on, the ex- NAND gate 20 then fed: back tothe other input of the elusive NOR inverts the input bit stream untilthe bi- NAND gate The output function of the binary Stet nary storageelement is reset age element 11 of FIG. 1 appears at the output of theThe foregoing operation of the binary storage ele- NAND g i g I ment maybe summarized by the following sequential The binary storageeiement 11of 1 functions in table: the following manner. The input bit stream from10 is applied to the inverter 14, which inverts the bit stream, andapplies the inverted bit streamm to the NAND gate Input BSE v BSE 15.The NAND gate 15 (by definition) functions in aci'g i l f i cordancewith the following truth table:

O l I 0 Inv. i 1 0 1 Bit NAND(20) NANDUS) 1 l l Stream Output Output Theoperation of the exclusive NOR may be summarized in the following truthtable: l 1 0 Input E I The succeeding transmission gate 16,. inverter17, Bit Xe Sive transmission gate 18, and inverter 19 successivel streamBSE NOR transfer the bit from the output of theYNAND gate 1% 0 0 lto'the input of the NAND gate 20 through .two inverg sions and two halfbit delays. 1 1 i The output bit stream from 10 then appears at theinput of the NAND gate 20 delayed one bit, and having gone through fourinversions, is uninverted.

The serial twos complementer whose block diagram Th NAND gate 20responds to h reset d control is illustrated in FIG. 1 may beadvantageously carried f n ti ns in addition to the delayed bit streamby a out in metal oxide semiconductor technology using sevth bl lik h fNAND gate 15, A i h eral preferences in the functional logical elemen lsare on the reset and control inputs, an inverted bit such as thepreferential use of NAND gates. The diafrom the bit stream, delayed onebit, will appear at the gram of FIG. 2 more fully describes such anembodioutput of the NANDgate 20. Assuming that the initial ment inconventional logical elements. bit is a 0, the NAND 20 output willproduce a 1 and the Referring to FIG. 2, the twos complementer com- 1will be fed back to the NAND gate 15 as assumed prises an inverter. 14,a NAND gate 15, a transmission previouslyvlf a second Obit occurs, thesame output at gate 16, an inverter 17, a transmission gate 18, an in-NAND gate20 will occur. If the third bit from the bit verter 19, and aNAND gate 20. All together, these elements perform the function of thebinary storage element ll of FIG. 1. The twos complementer is comstreamisa l'then the NAND gate 15 inverts as before (producing a zero) and theNAND gate 20 after a one bit delay, will have three one inputs, Causingits output to switch to a0, which is fed back to the NAND gate 15. Whenthe next bit comes along, the NAND gate 15 is unaffected by the signalon the bit and remains in the 1 state. The l is applied after a one bitdelay to the input of the NAND gate 20, which produces a 0 holding foreach succeeding bit, irrespective of the bit. Thus, the 0 outputcondition on the NAND gate 20 is held by this regenerative connectionthroughout the balance of the word, or until the reset, or twoscomplement control changes to a 0 condition.

The elements 23, 24 and 25 of FIG. 2 constituting the exclusive NOR gate12 of FIG. 1 are interconnected in the following manner. The NAND gate23, OR gate 24, NAND gate 25, each have two inputs and a single output.The input bit stream from is applied to one input of the NAND gate 23and to one input of the OR gate 24. The output of the NAND gate 20 isapplied to the other input of the NAND gate 23 and to the other input ofthe OR gate 24. The two inputs of the NAND gate 25 are takenrespectively from the output of the NAND gate 23 and the output of theOR gate 24. The output of the NAND gate 25 is the twos complement of theinput bit stream and is applied to the output 13 of the twoscomplementer.

The performance of the exclusive NOR function by the gates 23, 24, 25follows by consolidating their respective truth tables.

The exclusive NOR function is by definition:

The truth table for the NAND gates 23 and 25 are similar to that for theNAND gate 15 previously given. The truth table for the OR gate 24 is asfollows:

Bit NAND OR (24) Stream Output 1 Output I I 0 I l l The truth tables ofthe respective elements 23, 24

and 25 may be consolidated to explainthe operation of the exclusive NOR(12):

Bit NAND (20) NAND (23) OR (24) NAND (25) Stream Output Output OutputOutput I 0 l l 0 0 I I l O l I O l I number. The logic diagram of FIG. 2employs NAND gates throughout except for the single OR gate 24. Thelogic diagram is particularly advantageous in MOS technology being. ofminimum geometry. The function may be carried out using an area of 1.60X ID inches (l X 10' cm*) on a silicon chip.

The circuit implementation of the logic diagram of FIG. 2 is shown inFIG. 3. The circuit diagram illustrates the simple implementation of theforegoing logic diagram in providing the twos complement function. Theelements in the diagram are field effect transistors of the metal oxidesemiconductor variety. Suitable transconductances for the transistorsare illustrated in the chart of FIG. 4. The circuit functions arecarried out as follows: The transistor pair T1, T2 form the firstinverter 14; the transistor pair T7, T8 form the inverter 17; and thetransistor pair T10, T11 form the third inverter 19. The transistors T3,T4, T5 form the NAND gate 15; the transistors T12, T13, T14 and T15 formthe NAND gate 20. The transistors T6 and T9 form the transmission gates16 and 18, respectively. The foregoingperform the function of the binarystorage element 12 of FIG. 1. The transistors T16, T17, T18 form theNAND gate 23 and the transistors T19, T20, T21 and T22 together form theOR gate 24 and the NAND gate 25. The transistors (T2, T5, T8, T11, T15,T18 and T22), acting as load devices for the respective inverters andNAND gates, are of only 3 micromhos. The transistors performing theactive role in the NAND function and in the inverters are of a standard60 micromho transconductance. On the other hand, the OR gate 24 whichrequires serially connected transistors (i.e. T20, T21) requires thatwhen they are both on, they exhibit a joint transconductance of 60micromhos. Thus, T20 and T21 are required to be of twice thetransconductance micromhos) of the other transistors. Since an increasedtransconductance requires an increased area, the area requirement of theOR gate,'neglecting the small areas required for the load devices, isapproximately twice that of the corresponding NAND gate. In the presentconfiguration, an economy is effected since the NAND and OR functionsare combined in the four devices T19, T20, T21, T22 and one load deviceand one active device are aliminated. Thus, the transistor T22 jointlyacts as the load for the NAND function and for the OR function. Thetransistors T20 and T21 jointly act as the active part of the ORfunction and as one branch of the active part of the NAND function.

The input requires a 0 during the least significant bit time to returnthe binary storage element to its 1 complementary output state, and acontinuous l waveform during the remainder of the word time. The twoscomplement control requirement is of a similar nature in that acontinuous 1 enabling signal is required throughout the period whencomplementing is desired and a continuous 0 disabling signal is requiredthroughout the period when complementing is not desired. The change incontrol signal must occur at word boundaries. In both the case of thereset and of the control signal, time advance is not needed since thesesignals are applied directly to the NAND output gates T14 and T15 asshown in FIG. 3.

The logic diagram of FIG. 2 is implemented in the very simple andeffective fashion illustrated in FIG. 3. In addition to using a minimumof chip area (by preferential use of NAND gates and certain othersimplifications), the MOS structures used are simple and reliable.

storage ..configurations. f r

. The circuit does not have excessivepropagation dlays, allowing thechips to be usedwith high clock rates. The control and reset functionsallow the bit stream to continue without disturbing the contiguity ofthe data words.- What we claim as new and desire to secure by LettersPatent of theUnited States is: i I 1. Apparatus for serially forming thetwos complement of a binary number of variable word length, with theleast significant bit: first intime, and having a sign bit as the mostsignificant bit, comprising: t a. an apparatus input terminal to whichthe serial bi nary number is-applied, i

b. an apparatus output-terminal from which the complement is derivedf' I3 ,Apparatus;as setforthin claim 1 whereinisaid bi- .c. a binary storageelement having setand, reset connections and a complementary outputconnection, I I said set input connection being coupled to said ap paratus input terminal, said reset input connection being coupled toresetmeans to reset said binary storage element during the time of the leastsignificant bit for each word, k saidbinary storage element respondingto a 1 se signal and being clocked to produce a change 'in outputafter'a one bit delay,

anexclusi ,e NOR gate having two input connec tions andlan outputconnection,

,1 one input connection being coupled to said apparatus' irip'ut te'rjrninalythe other input connection b'eingfcoupledto the complementaryoutput of saidibin'ary storage element; and theoutput con- I riectionbeing coupled to said apparatus output terminal, I said exclusive NORgate inverting the bitstream at the apparatus input terminal when 'thecoinple-' mentary output of the binary storage element goes to the zerostate in response to a lin aserial binary number and producing a twoscomplement of said number at theapparatus output'ter "min al'. i i

2. Apparatusasset forth in claim 1 wherein said ex-' clusiveNOR gatecomprises:

a. a first NAND gate, a second NAND gate, and an I fOR'gate', eachhaving two inputs and an output, b. one input connection of saidfirstNAND g'ateand said OR'gate being connected to the output of saidbinary storage element, another input of said first NAND gate and ofsaid OR gate being connected to said apparatus input terminal,'outputconnections of said first NAND gate :and said OR gate being connected tothe respective inputs" of said second NAND gate and the output ofsaid-second NAND gate being connected to said apparatus output terminal.I l

nary storage eletne ntcomprises;

a. an inverter, a first I ,I Al, I D gatehaving two inputs and anoiitpug a dynamic one .bi t time delay, and

a second-NAND gatehaying twofinputs and an output,v b. saidinverterbeing :c oupled l )etween said apparatus input terminaione input of saidfirst NAND gate, the putput o f said'firstNAND gate being cou .pledthrough said time delay to one input of said secondNAND gate, the othersaid second NAND gate p rovidin g said'reset andthe out Y putofisaidsecon NANDgatebeing'coupled back tot he other in of saidfi'rstNANlDfgate and to the'input of, saidexclusive NOR Qgate'. v 4,.Apparatus as set forth' in claim einan input is provided to hold thebinary i'sto rage eleii1e rita.t the Zero state or; release thebinar ystorage element fdren; trolling the ,twos complementing processii i 5;Apparatus as set fo rth in clairn'4*"wherein said bi nary v a. an iverter, a; first gate 'hav'ing two inputs 'and-an'oi'itput', dynamicbrie bit time delayland a second NAND' 'gate' havingfthre'e inputsand'an gate, the output of said first gate being con:

pledthr ough said time dela'y 't'o one input of said second NAND gate, asecond input of said second NAND gate providing said reset input, andthe third input, of said second NAND gate providing said control input,and theoutpu-t of said second NAND gate bifiEcBii'pl'h bcl'i'm'i'hbihr'in'put of said first NAND gate and to theinput of said exclusiveNOR gate. 6. Apparatusasset forthin claim.5l.wherein said'gexclusive NORgate comprises: i

. a hi d NAND-sa ai urfih.NANQswe d an ,OR Hgate, each.haying twoinputsaan output, b. one input conneetionofisaid third Dgate and said OR gatebeing connected to the output of said binary storage element, anotherinput of said third NAND gate and of said OR gate being vconnected tqsikiv appa tu i iwt te m nal, .ou piut c nn tions of "said third NANDgate and said. OR gate being connected to the respective inputs of saidfourth'N AND gate and the output of said fourth NAND gate beingconnectedto said apparatus output terminal. .7. Apparatus assetforth inrclair'n-6 fabricated as a

1. Apparatus for serially forming the two''s complement of a binarynumber of variable word length, with the least significant bit first intime, and having a sign bit as the most significant bit, comprising: a.an apparatus input terminal to which the serial binary number isapplied, b. an apparatus output terminal from which the two''scomplement is derived, c. a binary storage element having set and resetinput connections and a complementary output connection, said set inputconnection being coupled to said apparatus input terminal, said resetinput connection being coupled to reset means to reset said binarystorage element during the time of the least significant bit for eachword, said binary storage element responding to a 1 set signal, andbeing clocked to produce a change in output after a one bit delay, d. anexclusive NOR gate having two input connections and an outputconnection, one input connection being coupled to said apparatus inputterminal, the other input connection being coupled to the complementaryoutput of said binary storage element; and the output connection beingcoupled to said apparatus output terminal, said exclusive NOR gateinverting the bit stream at the apparatus input terminal when thecomplementary output of the binary storage element goes to the zerostate in response to a 1 in a serial binary number and producing atwo''s complement of said number at the apparatus output terminal. 2.Apparatus as set forth in claim 1 wherein said exclusive NOR gatecomprises: a. a first NAND gate, a second NAND gate, and an OR gate,each having two inputs and an output, b. one input connection of saidfirst NAND gate and said OR gate being connected to the output of saidbinary storage element, another input of said first NAND gate and ofsaid OR gate being connected to said apparatus input terminal, outputconnections of said first NAND gate and said OR gate being connected tothe respective inputs of said second NAND gate and the output of saidsecond NAND gate being connected to said apparatus output terminal. 3.Apparatus as set forth in claim 1 wherein said binary storage elementcomprises: a. an inverter, a first NAND gate having two inputs and anoutput, a dynamic one bit time delay, and a second NAND gate having twoinputs and an output, b. said inverter being coupled between saidapparatus input terminal and one input of said first NAND gate, theoutput of said first NAND gate being coupled through said time delay toone input of said second NAND gate, the other input of said second NANDgate Providing said reset input, and the output of said second NAND gatebeing coupled back to the other input of said first NAND gate and to theinput of said exclusive NOR gate.
 4. Apparatus as set forth in claim 1wherein an input is provided to hold the binary storage element at thezero state or release the binary storage element for controlling thetwo''s complementing process.
 5. Apparatus as set forth in claim 4wherein said binary storage element comprises: a. an inverter, a firstNAND gate having two inputs and an output, a dynamic one bit time delay,and a second NAND gate having three inputs and an output, b. saidinverter being coupled between said apparatus input terminal and oneinput of said first NAND gate, the output of said first NAND gate beingcoupled through said time delay to one input of said second NAND gate, asecond input of said second NAND gate providing said reset input, andthe third input of said second NAND gate providing said control input,and the output of said second NAND gate being coupled back to the otherinput of said first NAND gate and to the input of said exclusive NORgate.
 6. Apparatus as set forth in claim 5 wherein said exclusive NORgate comprises: a. a third NAND gate, a fourth NAND gate, and an ORgate, each having two inputs and an output, b. one input connection ofsaid third NAND gate and said OR gate being connected to the output ofsaid binary storage element, another input of said third NAND gate andof said OR gate being connected to said apparatus input terminal, outputconnections of said third NAND gate and said OR gate being connected tothe respective inputs of said fourth NAND gate and the output of saidfourth NAND gate being connected to said apparatus output terminal. 7.Apparatus as set forth in claim 6 fabricated as a large scale integratedcircuit.
 8. Apparatus as set forth in claim 6 fabricated using metaloxide semiconductor field effect transistors (MOSFET) as the activedevices as a large scale integrated circuit.